Mile K. Stojčev

full professor

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Mile Stojčev

Academic career

  • Elected full professor in 1992 at the Faculty of Electrical Engineering in Niš, in the field of Electronics and Computer Science
  • PhD degree received in 1982 at the Faculty of Electrical Engineering in Niš, in the field of Electronics and Computer Science
  • Master degree received in 1977 at the Faculty of Electrical Engineering in Niš, in the field of Electronics and Computer Science
  • Bachelor degree received in 1970 at the Faculty of Electrical Engineering in Niš, in the field of Electronics and Computer Science

References

  • R21, M. Mitic, M. Stojcev, and Z. Stamenkovic, An Overview of SoC Buses, in Embedded Systems Handbook, Digital Systems and Aplications, V. Oklobdzija (Ed.), chapter 7, CRC Press, Boca Raton, 2008, pp. 7.1- 7.16
  • R51-b, M. Stojcev, G. Jovanovic, Clock Aligner Based on Delay Locked Loop with Double Edge Synchronization, Microelectronics Reliability, 2008, Vol. 48, No. 1, pp. 158-166.
  • R51-b, M. K. Stojčev, G. Lj. Djordjevic, T. R. Stanković, Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits, Microelectronics Reliability, Vol. 44, Issue 1, Elsevier, January 2004, pp. 173-178
  • R51-b, Krstic M.D., Stojcev M.K., Djordjevic G. Lj., Andrejic I.D., A Mid-Value Select Voter, Microelectronics Reliability, Vol. 45, pp.733-738, 2005
  • R52, Djordjevic G.Lj., Stojcev M.K., Stankovic T.R., Approach to partially self-checking combinational circuit design, Microelectronics Journal, Vol. 35, No. 12, pp. 945-952, December 2004
  • R52, Goran S. Jovanović and Mile K. Stojčev, Current starved delay element with symmetric load, International Journal of Electronics, Taylor & Francis Publisher, Volume 93, Number 03 / March 2006, pp. 167 – 175
  • R52, Goran Jovanović, Darko Mitić, Mile Stojčev, An adaptive pulse-width control loop, International Journal of Electronics, pp. 291 - 311, Vol. 93, No. 5, May 2006
  • R52, M. K. Stojčev, G. L. Djordjević, E. I. Milovanović, I. Z. Milovanović, Data reordering converter: an interface block in a linear chain of processor arrays, Microelectronics Journal, 31 (1) (2000), 23-37

Activities

  • Total number of papers in journals with IMPACT factor: 32
  • Current involvement in projects: National: 2; International:
  • Other relevant information:

Contacts us

Address: Aleksandra Medvedeva 14, 18106 Niš

Phone: +381 (18) 529-105

Fax: +381 (18) 588-399

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PIB: 100232259

Account number: 840-1721666-89