Goran Lj. Đorđević

full professor

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Goran Đorđević

Academic career

  • Elected full professor in 2009 at the Faculty of Electrical Engineering in Niš, in the field of Electronics
  • PhD degree received in 1998 at the Faculty of Electrical Engineering in Niš, in the field of Electronics
  • Master degree received in 1994 at the Faculty of Electrical Engineering in Niš, in the field of Electronics
  • Bachelor degree received in 1989 at the Faculty of Electrical Engineering in Niš, in the field of Electronics

References

  • Milica D. Jovanovic, Goran Lj. Djordjevic, “Reduced-Frame TDMA Protocols for Wireless Sensor Networks”, International Journal of Communication Systems, John Wiley & Sons, Ltd., ISSN: 1099-1131, 2012, DOI: 10.1002/dac.2439, accepted for publication.
  • A. S. Velimirovic, G. Lj. Djordjevic, M. M. Velimirovic, M. D. Jovanovic, “Fuzzy ring-overlapping range-free (FRORF) localization method for wireless sensor networks”, Computer Communications, Elsevier Ltd., ISSN 0140-3664, Vol. 35, No. 13, 2012, pp. 1590-1600, DOI: 10.1016/j.comcom.2012.05.006.
  • T. R. Nikolic, M. K. Stojcev , G. Lj. Djordjevic , “CDMA bus based on-chip interconnect infrastructure”, Microelectronics Reliability, Elsevier Ltd., Vol. 49, No. 4, April 2009, pp. 448–459, DOI: 10.1016/j.microrel.2009.02.002.
  • M. D. Krstic, M. K. Stojcev, G. Lj. Djordjevic, I. D. Andrejic, „A Mid-Value Select Voter“, Microelectronics Reliability, Elsevier Ltd, Vol. 45, No. 3-4, pp.733-738, March-April 2005. DOI: 10.1016/j.microrel.2004.07.006.
  • G. Lj. Djordjevic, M. K. Stojcev, T. R. Stankovic, „Approach to partially self-checking combinational circuit design“, Microelectronics Journal, Elsevier Ltd, Vol. 35, No. 12, pp. 945-952, December 2004. ISSN: 0026-2692. DOI: 10.1016/j.mejo.2004.07.007.
  • M. K. Stojčev, G. Lj. Djordjevic, T. R. Stanković, “Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits”, Microelectronics Reliability, Vol. 44, No. 1, Elsevier Inc, pp. 173-178, January 2004. ISSN: 0026-2714, DOI: 10.1016/S0026-2714(03)00377-9.
  • M. K. Stojcev, G. Lj. Djordjevic, M.D. Krstic, “A hardware mid-value select voter architecture”, Microelectronics Journal, Vol. 32, No. 2, pp. 149-162, 2001. ISSN: 0026-2692. DOI: 10.1016/S0026-2692(00)00114-2.
  • B.Vasic, G. Lj. Djordjevic, M.Tosic, “Loose Composite Constraint Codes and Their Application in DVD”, IEEE Journal of Selected Area in Communications, Vol. 19, No. 4, pp. 765 –773, April 2001. ISSN: 0733-8716. DOI: 10.1109/49.920184.
  • M. K. Stojcev, G. Lj. Djordjevic, E. I. Milovanovic, I. Z. Milovanovic, “Data reordering converter: an interface block in a linear chain of processing arrays”, Microelectronics Journal, Elsevier Inc, Vol. 31, No. 1, pp. 23-37, 2000. ISSN: 0026-2692 DOI: 10.1016/S0026-2692(99)00086-5.
  • M. Tosic, M. Stojcev, D. Maksimovic, G. Lj. Djordjevic, “The asynchronous counterflow pipeline bit-serial multiplier”, Journal of System Architecture, Elsevier B.V, Vol. 44, No. 12, pp. 985-1004, 1998. ISSN: 1383-7621.DOI: 10.1016/S1383-7621(97)00046-5.
  • G. Lj. Djordjevic and M. B. Tosic, “A heuristic for scheduling task graphs with communication delays onto multiprocessors”, Parallel Computing, Elsevier Science B.V., Vol. 22, No. 9, pp. 1197-1214. 1996. ISSN: 0167-8191. DOI: 10.1016/S0167-8191(96)00041-5.
  • G. Lj. Djordjevic, M.B. Tosic, “A compile-time scheduling heuristic for multiprocessor architectures”, The Computer Journal, Oxford University Press,Vol.39, No.8, pp 663-674, 1996. ISSN: 0010-4620.DOI: 10.1093/comjnl/39.8.663

Activities

  • Total number of papers in journals with IMPACT factor: 12
  • Current involvement in projects: National: 1; International:
  • Other relevant information:

Contacts us

Address: Aleksandra Medvedeva 14, 18106 Niš

Phone: +381 (18) 529-105

Fax: +381 (18) 588-399

e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

PIB: 100232259

Account number: 840-1721666-89